1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and an operating method therefor, and more particularly to an electrically programmable metal-oxide-semiconductor (MOS) type read only non-volatile semiconductor memory device and an operating method therefor.
2. Description of Related Art
Generally, in a semiconductor memory device such as a read only memory (which is hereinafter referred to as a ROM) or the like, high-density formation is required, and for this requirement, a virtual ground structure of a non-volatile semiconductor memory device is conventionally proposed. The virtual ground type memory structure is a known technique capable of enhancing the integration density of memory cells in an array while maintaining compatibility with the n-channel process and a two-layered gate electrode structure formed of ordinary two-layered polysilicon.
An EPROM (Erasable and Programmable ROM) of virtual ground structure shown in FIGS. 3 and 4 is published in IEEE Electron Device Lett, vol. 12, p. 450, 1991 and the array structure proposed in the cited publication is made such that one metal bit line is arranged for two interconnection layers formed of buried diffusion layers of virtual ground structure, and a memory cell is selected by use of an adequately arranged selection transistor. In this array structure, as a typical example, the EPROM cell is programmed by applying 12 V to the gate, applying 7 V to the drain, grounding the semiconductor substrate and source, and injecting channel hot electron into the floating gate.
The conventional non-volatile semiconductor memory device and the operating method therefor are explained below with reference to FIGS. 3 and 4.
FIG. 3(a) shows an equivalent circuit of the EPROM. FIG. 4 is a plan view showing the outline of the arrangement of the non-volatile semiconductor memory device. FIG. 4(b) is a cross sectional view taken along the line X-Y of the above plan view, and the same symbols are attached to the same portions.
FIG. 3(a) shows a plurality of memory transistors (which are hereinafter simply referred to as memory cells) 1, 1a, 1b each having a floating gate 2, and the control gates thereof are connected to a word line 3. Buried diffusion layers (bit lines) 5, 5a function as drains for all of the memory cells and buried diffusion layers (bit lines) 4, 4a, 4b function as sources.
Each memory cell includes the floating gate 2, the control gate 3 connected to the word line, and buried diffusion layers functioning as the source and drain, and the non-volatile semiconductor memory device is constructed by two bit lines 4 and 5, formed of buried diffusion layers, a metal line 6 arranged for every two bit lines, selection transistors 7 and 8, and selection lines 9 and 10 connected to the gates of the selection transistors 7 and 8.
The arrangement of the array structure of the non-volatile semiconductor memory device of FIG. 3 is shown in the plan view of FIG. 4(a), memory cells are arranged in a matrix form, and FIG. 4(b) shows the cross section of the array structure. The buried diffusion layers 4, 5, 4a, 5a are formed in parallel and covered with an insulation layer. The word lines 3 are arranged to intersect the buried diffusion layers at right angles. Generally, the word line 3 is formed of a conductive polysilicon layer.
Further, it is known that in the conventional flash memory of array structure which is the array structure other than the so-called virtual ground structure, both of the programming and erasing operations can be attained by use of a single power supply of low voltage by using a Fowler-Nordheim tunnel current. Particularly, in the array structure called a NOR type, the function of the flash memory can be provided by the programming and erasing operations by the Fowler-Nordheim tunnel current by defining a state in which excessive electrons are stored in the floating gate, that is, a state in which the threshold value is as high as the erasing state.
That is, in order to lower threshold value or to program the memory cell set in the erasing state in which the threshold value thereof is high, a power supply voltage of 5 V, 3.3 V or the like is applied to one of the drain and source, the other electrode is set in the floating state, the semiconductor substrate is grounded and a negative voltage is applied to the gate. Under this condition, a high voltage is applied to a gate oxide film at one end of the drain or source so that the electrons stored in the floating gate can be drawn as a tunnel current, thereby lowering the threshold value of the memory cell and programming the memory cell. At this time, it is important that a desired memory cell can be independently selected by adequately selecting the word line and bit line.
Further, since consumed current is smaller in the programming by the Fowler-Nordheim tunnel current than in the programming operation by channel hot electron, it is possible to independently select the bit lines of a group of memory cells which commonly have a selected word line as a control gate and effect the programming operation in parallel.
Further, the erasing operation can be effected by applying a high voltage to the gate and grounding the semiconductor substrate or applying a negative voltage thereto so as to cause a tunnel current via the gate oxide film of the channel portion, inject excessive electrons into the floating gate, and enhance the threshold value. This operation is simultaneously effected for the whole chip or for all of the memory devices in the block, thereby making it possible to provide the function of the flash memory.
At present, the power supply for electronic devices tends to be provided by a single power supply of low voltage of 5 V or 3.3 V , and in this situation, there is a problem in the EPROM or flash memory using the virtual ground type array structure as shown in FIG. 3(a). That is, when the programming of the virtual ground type array structure is effected by channel hot electrons, a high voltage is applied as a voltage applied to the drain and a large current is required. Virtual ground type flash memory it has a disadvantage that it is not suitable for usage of the single power supply of low voltage (5 V or 3.3 V).
Further, in the array structure of FIG. 3(a), the bit line 4 always functions as a source for each memory cell and the bit line 5 functions as a drain, and it is impossible to effect the programming or erasing operation by the Fowler-Nordheim with the above symmetry being kept.
For example, when the memory cell in 1b is to be programmed, it is necessary to apply a power supply voltage to the bit line 5a and apply a negative voltage to the word line 3, but this condition is simultaneously applied to a memory cell 1c which lies in position symmetrical to the memory cell 1b via the bit line 5a as the programming condition.
Likewise, when the programming is effected by applying a potential to the source 4a of the memory cell 1b, the potential is also applied to the source of the memory cell 1a and it is impossible to separately program the two adjacent cells.
It is impossible to effect the programming by the tunnel current while the memory cells are kept in the symmetrical relation. Assume now that the bit line 4a shown in FIG. 3(b) functions as a drain for the memory cell 1a and functions as a source for the memory cell 1b, and that the arrangements of the drains and sources of respective memory cells have the symmetry in which the sources and drains are all made in the same direction as shown in FIG. 3(b). In order to program the memory cell 1a, a power supply voltage is applied to the bit line 4a and a negative voltage is applied to the word line 3. The bit line 4a applies a voltage to the memory cell 1b, but since it is connected to the source of the memory cell 1b, it is possible to independently program the memory cell 1a.
However, in order to program the memory cell 1b, it is necessary to apply a power supply voltage to the bit line 5a on the drain side thereof, but since the bit line 5a is not directly connected to a metal line, the power supply voltage must be supplied from the metal line 6a or 6b via the selection transistor 7 or 8. That is, in this case, a voltage is applied to the bit line 4a or 4b to set up the programming condition for the memory cell 1a or 1c. Therefore, it is impossible to independently program all of the memory cells. In the virtual ground array structure, since the potential of the metal line 6 is always applied to the buried diffusion layer 4 irrespective of the state of the selection transistor, it is impossible to independently select the buried diffusion layer 5. That is, in the non-volatile semiconductor device of FIG. 3(a), it is impossible to effect the programming by the tunnel current.
That is, the bit lines formed of the buried diffusion layer in the array structure include bit lines which are directly connected to the metal line and bit lines which are connected to the metal line via the selection transistor. In order to program the memory cell by the method using the tunnel current, a potential must be independently applied to the memory cell. However, in this array structure, when a potential is applied to the bit line 5, the same potential is inevitably applied to at least the bit line 4 and it is impossible to independently program the memory cells.
Further, not only in the EPROM or flash memory, but also in general, a leakage current caused at the readout time should be given as a problem of the memory of the virtual ground type array structure. That is, in the virtual ground type array structure, there is a possibility that a leakage current will flow in a direction of the bit line opposite to a flow of ordinary readout current into the source side from the bit line acting as the drain at the readout time and the readout characteristic of the memory cell will be degraded.